1. Field of the Invention
This invention relates to a three-dimensional semiconductor integrated circuit (IC) and a method for manufacturing the same. More particularly, the three-dimensional semiconductor IC of the present invention comprises a unit semiconductor IC, which has ICs formed on both surfaces of a substrate. The unit semiconductor IC has a plurality of conducting posts which are buried in and extend to both surfaces of the substrate. The conducting posts are insulated from the substrate. The unit semiconductor IC also has interconnection terminals for connecting other unit semiconductor ICs to both sides of the substrate. By stacking plural unit semiconductor ICs on a base plate, a very large scale IC can be manufactured. The structure of a single unit semiconductor IC according to the present invention can also be used for a PROM or MASK ROM structure.
2. Description of the Prior Art
Conventional ICs are formed on a surface of a silicon substrate. A high integration is achieved by enlarging a chip area employing a two-dimensinal method which includes making each individual element small and each wiring fine. The above two dimensional method has limitations in wafer process technology. Accordingly, three-dimensional ICs have been proposed.
The technology under development regarding three-dimensional ICs is mainly concentrated on SOI (silicon on insulator) technology. As an example of SOI technology, an insulating film is grown on a main substrate by a CVD (chemical vapor deposition) or a thermal oxidation method, and then a polysilicon layer is deposited thereon by CVD. The polysilicon layer is laser-annealed resulting in a recrystallization thereof and single crystal regions are partly formed. Upper semiconductor elements are then formed on the single crystal regions.
This method, however, has a problem in that a silicon crystal of high quality having very few grain boundaries cannot be grown with a good reproducibility. Consequently, the production process of a three-dimensional IC having a multilayer SOI structure has a very low yield rate.
Another prior art method for making a three-dimensional IC has been disclosed in "Promising New Fabrication Process Developed for Stacked LSIs", M. Yasumoto et al., IEDM, 1984, pps. 816-819 and is shown in FIG. 1.
In FIG. 1, two separate IC chips 201 and 201' are provided, each having contact pads or terminals 202 or 202' formed on a first surface of a substrate on which each IC (201, 201') is formed. Two chips are assembled as a single stacked three-dimensional IC by turning over IC chip 201' and stacking it on IC chip 201. These two ICs are adhered to each other using the contact pads or terminals (202, 202'). In FIG. 1, regions 203 and 203' are constituent ICs for each IC chip. The two IC chips are bonded together with the aid of insulating and adhesive layers 204 and 204'. This method is applicable only when two IC chips are stacked together.